Microprogrammable i/o controller

ABSTRACT

A microprogrammable plural ALU (arithmetic-logic unit) controller utilizes task assignments for improving processing efficiencies. The ALU&#39;&#39;s are selected to be low-cost, lowcapability devices. Each ALU is within one independent Micro Programmable Unit (MPU). Interconnection registers, preferably symmetrically arranged, provide program synchronization between the plural MPU&#39;&#39;s. These same registers have direct connections to data flow circuits for monitoring and controlling their operation.

O Unlted States Patent [1 3,654,617 Irwin 1 Apr. 4, 1972 1541MICROPROGRAMMABLE [/0 3,469,239 9/1969 Richmond et a]. ,,...340/172.5CONTROLLER 3,409,880 11/1968 Galler .340/1725 3,408,632 10/1968 Hauck340N725 m] 3,411,143 11/1968 BeaUSOiCll et al. Mam/172.5 [73] Assignee:International Business Machines Corpora- 3 12/1963 M 1 a] 4 t r 4 /l72.5tlon, Armonk, NY. 3,500,328 3/l970 Wallis ..340/l72.5

[22] led: 1970 Primary Examiner-Paul.l. Henon [2]] Appl. No; 77,088Assistant Examiner-Ronald F. Chapurah A1l0rney--Hanifir1 and Jancin andHerbert F. Somermeyer [52] U.S.Cl ..340/l72.5 51 int. 131 ..c0619/121571 ABSTRACT [58] Field ofSearch ..340/l72.5 A microprogrammabk p|ura1ALU (arithmetiologic unit) controller utilizes task assignments forimproving processing [56] References Cited efficiencies. The ALU's areselected to be low-cost, low-capa- UNITED STATES PATENTS bility devices.Each ALU is within one indeoendent lviicro Programmable Unit (MPU).interconnecnon reg1sters, 3,210,733 [0/1965 Terzian et al ..340/l72-5preferably symmetrically arranged, provide program 3.2381506 3/1966 g Bl5 synchronization between the plural MPU's. These same re- 2 1 1012/1960 EPlimsoll at 340/172 5 gisters have direct connections to dataflow circuits for moni- 3 ,3 i i Hertz t ...340/172.5 {oring andcontrolling their operation 3,377,623 4/1968 Rent at al. ..340/l72.53,395,396 7/ l 968 Pasternar ..340 72.5 20 Claims, 37 Drawing FiguresINFORMATION "S /stat m INYERFACE Y F it 7 7 i 7 v 111s 1/0 27 CONTROLLERBUFFER SYSTEM Patented April 4, 1972 26 Sheets-Sheet Patented A ril 4,1972 3,654,617

26 Sheets-Sheet S BUS 0 I81 REGISTER REGISTER Z11 ll/Il/l/[l I I I4llllll/II/ I; 2 D B Emm (xmm A 9a; (xaxm A 82 a5 msmucmfi 72 as DECODEEXCHANGE A H 84 B BUS REGISTERS 11/1111? 7 REGISTER ,& 0 T5 ,LJ

s E HUS LSR' E 2 86 III, I, I], 2 ll/ll/lI/l/ [I] l I WL J III/ III] 114]15 I, TRANSFER /74 z I 68 emnsmucnou 1 m; 5 5 REGISTER new 1 BRANCH 20m rLowsm CONTROL I B- 1 [/1 1/1/11 1/1/11] j E A :1 65' R05 j E ADDRESSB00 2 comm cum 2 MEMORY CIRCUIT I I III/I I, l 66 m 2 L0 g \msmucnou mIIIIIIIIIII/IIIIIIIIIII REGISTER A W uc) 99A 98 1 HOLD 5 =]|CL0CK|L- W8I TRAP A eo A mm ADDRGO 8k smus REGISTER a A m -m BRANCH comm (OTHERMPU) L0 -ano smn Patented April 4, 1972 3,654,617

26 Sheets-Sheet 4 "RF RRF BUFFER GENERATOR PE&NRZ|

m TIMING AND TACH comm cmcuns 5s a 50 11s a m 35 BUFFER PUD BUFFER STOREm STORE u z 51 a2 FAcH 8 IDLESCAN IDLEPEND CHECK -+R0F CHAINED (H619)PENDING smus FFRRsFAK(F|c* 19) WAIT FOR DPfl|IiE SELECTION f F CHNL TRAP0mm EXECDEHHGSFSJU (FIG. 15) FRRP MPUY /MPUY 5m E STATUSTERMSTAT(FIG.18) MPUX I (H612) I |NTERRUPT--..\4' SCAN l t MM M MPUYSTAT i l mu ADDR (FIG. 12) i l I TRAP MPUY FULL I INTFY uFcP0LL(F|R14) I(Hm) I J MPUY am I Patented April 4, 1972 3,654,617

26 Sheets-Sheet 6 mm (r us 10) [XECDEP wux a Y-DEPRIME smr (H611) \155 L#"m m 43) EXECPOLL Y-POLL MPUX INTFY STAT (H614) 1 i POLL MTIX Y- um SELFIG 26) MPUX 0F F 486 STMC EXECUES CLEAR mzsn DEPRIME J FIG. 44

SET 5m 0 WAIT MPUX F G DE PR m5 (me A 8 SET mu END 0LEARSTAT RESET SETsm 5 sm 6 4 16 YES RESERVED N0 TRAP MPUY mp EXECDEP IPUY (FIG. 4 4

i OTHER Pens,

Patented April 4, 1972 3,654,617

26 Sheets-Sheet 7 DEP: DEVICE END PRIME m2 m0 mu \4 ms \swncuso FJ; KSEIE 'W RESET ADDR a smc COUNT mu YES SCA N0 ausv none sw YES SE SET sm0 (F g l fl SIMON MPUY POLLMTIX (FIGS) Patented A ril 4, 1912 MTU ADDRT0 LSR 26 Sheets-Sheet 8 FROM (H010) 187 188 192 0" MPJY 1a9 SW0? MPUY5m FETCH MPUY (Hem mu RonR SW D? REG YA OFF mu ADDR H1223 RPuY YESSELECT MTU mm 9 DIAS m 195 SET 5W0 RESERVED?/196 isoQ HPUY ON ON SIHTUY7 sure? 0 MPUY sma? MPUY orr sm 0? i MPUY YES ERROR YES RESERVED? SET sm9 smr a? L OFF POLLMTI TRAP MPUY LIM (new (new: SET 0 FLAG PatentedApril 4, 1,972

26 Sheets-Sheet 9 POLLMTI FIG.|3

AND STATUS 200/ CONTROL EXECPOLL (FIG 14) SET SUPP REO IN ALL CHNL EEISUPP RED m on IDLEPEND (FIG 8) Patented April 4, 1972 26 Sheets-Sheet 10EXECPOLL CLEAR LSR P 206 I SET smn win MPUX FIGJS TRAPMPUX FROM INIFX ISTDRE smusK INITIALIZE GENRST SELRST I FIG 24 I IN SELCHK I Fl 6 I6 IDIAC I27 I FIG 24 I Patented April 4, 1972 FIGJG FIG.

DROP ADDRES IN TAG 26 Sheets-Sheet 1 l INSELCHK CHECK PULLED (FIG. 17)

22r- INTTIAL TERMSTAKTFICJQ) IDLESCAN (ma) -|N|r|NuzE ERROR (NEW ADDR)FETCH COMMAND WWI) MODETYPE (H024) I L CMD REJECT (H6519) TU TEST (FIG.20)

POLLED CHECK STATUS SET UP IN ON CTI DETERMINE WHICH 254 CHANNEL ISPOLLING VERIFY Q STATRTN (FTCTB) A D D R E S S HIONOP FIG. T9)

AND CMDPARER (no. 25) COMPARE DIAGNOSE (FIG. 24)

TERMINATE (H019) INITIAL couomons 0K READTYPE (m;v 20 DECODE WRTCHECK(FIG. 21)

Patented April 4, 1972 26 Sheets-Sheet 12 FIG.48

CLEANIT CLEAR STATUS XSR I STATRTN if I {238 INTFX YES TERMSTAK (FIG 19SET ,STACK TERMSTAK BRANCH LINK 1 TERMACC (FIG 49) Patented April 4,1972 26 Sheets-Sheet l3 CMDPARER CMDPAR 1 CMDRJT TERMSTAT I /248lNTFX-SET 255 247 cREcR N0 PENDING mm mm INTFX smus, TO

SET m smus IDLESCAN 256 UNIT 249 STATUS YES cRR sm PEND UNITCHK SET SETSUPP sm PEND BUSY 251 REG m mcs 251 STATRTN RDLEPEND (new 1 (FIGBJTERMACC RESET 260 wcomo TERMSTAK TERMSTK 1 HIONOP (FIG 24) cRRmEn YES 1l CONDITIONAL CONNECT STSAETTUS RESERVED LINE +-H- NO I CLEAR sm RESETmm TRAP MPUY CL EAR mu FOR mm T0 DESELECT 69 I IDLESCAN i (FIG 8 TRAPuPuv ITO DESELECT YES FIG.2O

SET LINK 1 I10 INTERPRET SENSE TERHSTAT COMMAND 5 19) PROTEST YES 2T4COMRJECT 272 (FIG.19)

HPUYC YES CMDPAR 1 BRANCH LINK 1 CLEANED 501 PRESET 502 YES WRIIE YESHPUY 0 M10 3 5 REM) BSTWMT (FIG. 23)

Patented April 4, 1972 3,654,617

' 26 Sheets-Sheet 15 WRITE INITIALIZE FIG. 21

m1 WRTFST SET BRRRcR: i 280 LINK u-vmrsr J LINK z-wcosrP LINK S-WCOHIOmum OOTIEM5\ 284 T up '(FIGZR;

i CLEAR mp REGISTERS 282 my WRITE SVCRTN HQ (H622) vEs ERRoR srs YES(FIG 23) TAPE OF 235 YES 28?] N0 MPUY /-2 3 5W0 umcuosnc SW 0 YES 1E sHIOPERG MPUY DDR0 YES ERRORSTS ABORT 155 SET umr CHDO CHECK I nPuv YES286 STAT 0 J No SE F BSTWA T I SIOP ms 25) D'ABNOST'C SERVRTN YES BRANCHYES *LRNR 3 2m cm YES SET 288 svc m YES 239/ ADDRO YES Moo WNL s EavoM290 SET BRANCH YES STOP LINK 2 BRANCH LlNKi Patented April 4, 19723,654,617

26 Sheets-Sheet 16 HIOPERG SET STOP 29s RESCHAIN RES on ausv HOLDBSTWAIT Ammo YES 292 ADDRO cum) SET STOP mo nPuv HPUY YES ALU ERR HPUY5H J EXCEPT YES SENSE "Pm no uun V YES SENSE SEI FLAGS TERMSTAT (new)WCOSTOP 00mm 299 SET OTHER SENSE ERROR 298 can AND W SENSE SET PatentedApril 4, 1972 3,654,617

26 Sheets-Sheet 1? oosfusfi FIG 24 SEND CLEAN 505 smus TRAP MPUY SENSESET BRANCH FIG. 56) LINK IN LSR FETCH BYTE SERVRTN BRANCH LINK 1TERMSTAT SERVRTN HC. 22

Patented April 4, 1972 EXECSTS FETCH MTU ADDR OFF ACTIVE CHECK DEV 26Sheets-Sheet l8 MPUX TRAP FETCH XA ENTER SPECIHED ROUTlNE Fl G. 2 6

FETCH "TU SENSE BYTES BYTES To YA & YB SET STAT C ENDUP (H027) WAIT FORMPUX Patented April 4, 1972 3,654,617

26 Sheets-Sheet 19 FIG.27

RESET TAPE OP FETCH HTU SENSE CHECK AND LOG ERROR CONDITIONS FIG. 28 SETsmn MTI SEARCH WAIT MPUX OFF CHECK DEV (H026) OFF FETCH SENSE FROM MTUsma CLEAR MTU TAGS RESET INTFY SWITCH CONNECTION SET STAT D 540 T WAITMPUX

1. A microprogrammable I/O controller adapted to control a pluralitY ofI/O devices in response to controlling system sets of instructions andprocessing information-bearing signals therebetween, the improvementincluding the combination: a plurality of independently operablemicroprogrammable units (MPU''s); each MPU having its own program ofmicro-instructions, a set of output exchange registers (A, B), and inputgating means receiving signals from said exchange registers of all otherMPU''s and selectively opened in accordance with the respective MPUprogram of micro-instructions; and data flow means receiving signalsfrom said exchange registers and responsive thereto be performsignal-processing operations including signal waveform modifications forchanging information representing characteristics in accordance withsignal patterns in said exchange registers for exchanginginformation-bearing signals between said controlling system and said I/Odevices.
 2. The combination of claim 1 wherein each MPU has a computingcapability substantially less than that required for singly controllingsaid data flow means, controlling said I/O devices and responding tosaid sets of instructions; and all of said MPU''s being identicallyconstructed except for the respective programs of micro-instructions. 3.The combination of claim 1 wherein said data flow means has an MPU toprocess said information-bearing signals in accordance with its programof instructions and being responsive to signals in said exchangeregisters from said MPU''s not in said data flow means for performingsaid signal-processing operations.
 4. A microprogrammable I/O controlleradapted to control a plurality of I/O devices in response to controllingsystem sets of instructions and for processing information-bearingsignals therebetween, the improvement including the combination: aplurality of independently programmable microprogrammable units(MPU''s), a set of output exchange registers for interconnecting saidMPU''s and input gating means in each MPU receiving signals from saidexchange registers from the other MPU''s and each MPU selectivelyopening said gating means in accordance with the MPU program ofinstructions, one of said MPU''s (MPUX) being connected to saidcontrolling system for exchanging control signals and data signalstherewith and for coordinating transfer of signals between said dataflow means and said controlling system, a second one of said MPU''s(MPUY) being connected solely to said I/O devices for coordinatingoperation thereof with said data flow means, and an I/O device addressregister in said controller and connected to MPUX for transferring I/Odevice address signals from MPUX to said I/O devices for activating samefor operation with MPUY and said data flow means.
 5. The combination ofclaim 4 wherein said data flow means has data-signal writing means anddata-signal reading means respectively for supplying signals to and fromsaid I/O devices, one of said output exchange registers of MPUY(register YA) being connected primarily to said read detection portionand one of said output exchange registers MPUX (register XA) beingconnected primarily to said write control circuits; MPUX and MPUY eachhaving status registers; and command means in said data flow meansjointly responsive to signals in said status registers and to signals inregisters XA and YA respectively of MPUX and MPUY for initiating andcontrolling signal-processing operations in said data flow means.
 6. Thecombination set forth in claim 5 wherein said data flow means includesdata flow sense registers having signals indicating operational statusthereof, means in said data flow means jointly responsive to statussignals from MPUX and to signals from register XA to transfer sensebytes from said sense registers to said controlling system.
 7. Thecombination of claim 5 wherein register YA supplies its signals directlyto said data flow means unconditionally imposing operational conditionsthereon in accordance with the signal pattern therein; register XA beingselectively gated to said data flow means by said status registers ofMPUX and MPUY for selectively altering operational status of said dataflow means such that said output register of MPUX may be used jointlyfor transferring instructional signals to MPUY and said data flow means;and MPUX monitoring signals in register YA.
 8. The combination of claim4 wherein MPUX output exchange registers are XA and XB and wherein MPUYoutput exchange registers are YA and YB, said registers XA and YA beingconnected to said data flow means and registers XB and YB beingconnected only to MPUY and MPUX, respectively; status registers in eachMPUX and MPUY; and branch control means in each MPUX and MPUY receivingsignals from status registers of MPUY and MPUX, respectively, and saidmicroprograms in MPUX and MPUY coordinating operations in accordancewith the status signals in said status registers and MPUY branching tomicroprograms in accordance with signals in register XA.
 9. Thecombination of claim 8 wherein programs in MPUX during an initialselection by said controlling system provide coordination between theI/O controller and the controlling system; programs in MPUY respondingto said MPUX programs for polling the status of attached I/O devices;and programs in MPUX selecting an I/O device being polled by MPUY, saidMPUY supplying status signals to MPUX for either selecting ordeselecting an I/O device and indicating same to MPUX via said exchangeregisters.
 10. The combination set forth in claim 4 wherein MPUX andMPUY each have a plurality of independently performable microprograms;MPUY including instruction counter means presettable to a predeterminedinstruction within a program of instructions; MPUX forcing said MPUYinstruction counter to said one number and simultaneously providing areference to a given program of instructions in said exchange registers,said MPUY executing a program of instructions in accordance with saidinstruction counter to obtain the reference to a given program ofinstructions from said exchange register and then executing said givenprogram; and MPUY having timing pulse means and means further operativeupon completion of said given program of instructions to stop saidtiming pulse means until MPUX again inserts a number into saidinstruction counter of MPUY.
 11. A data channel controller having firstand second interface portions, each portion having different signalformats, data flow circuits electrically interposed between saidportions and operative to alter information-bearing signals inaccordance with said signal formats whereby signals may be exchangedbetween said portions, the improvement including the combination: aplurality of MPU''s (microprogrammable units), each MPU having a memory,an input and an output portion; first and second of said MPU''srespectively operatively associated with said first and second interfaceportions and being programmable to exchange control and data signalstherewith; first and second sets of exchange registers respectivelyconnected to said first and second MPU''s for receiving result signalstherefrom and supplying said result signals to said data flow circuitsfor controlling same to alter said information-bearing signals; andfirst and second gating means respectively controlled by said first andsecond MPU''s for gating said result signals from said second and firstexchange registers respectively into said first and second MPU''s. 12.The combination set forth in claim 11 wherein said first MPU isoperative to sample one of said exchange registers of said second MPUwhile said one exchange register is supplying signals to said data flowciRcuits for monitoring operation thereof whereby said first MPUexercises simultaneous supervisory control over said second MPU and saiddata flow circuits such that programming coordination between said firstand second MPU''s is effected.
 13. The combination set forth in claim 11further including a third MPU is said data flow circuits being jointlyresponsive to said first and second MPU''s to perform signal-processingoperations in accordance with signals received from said first andsecond sets of exchange registers.
 14. The combination set forth inclaim 11 wherein a plurality of record-media transporting devices areconnected to said second interface portion and being responsive toaddress signals for initiating an active condition, and said first MPUhaving an address register connected to all of said record-media devicesfor addressing same and all other connections between said controllerand said record-media devices being through said second MPU and saiddata flow means.
 15. An I/O controller having first and secondmicroprogrammed MPU''s (microprogrammable units) each performingdifferent but functionally related program operations and supplyingcontrol signals to interconnecting register means; data flow circuitsreceiving said control signals from said register means having first andsecond portions respectively primarily responsive to said MPU''s toperform signal-processing operations including changing signalinformation representation while maintaining information content; andsaid first and second MPU''s receiving said control signals undermicroprogram selection from said register means and being responsivethereto for coordinating said signal-processing operations in said dataflow circuits and operations of said microprograms.
 16. The controllerset forth in claim 15 having quiescent periods wherein said data flowcircuits are processing no signals, the combination further including: astat C and D means in each MPU supplying status signals to the otherMPU, trap means in the second MPU to select a given microprogram inresponse to a trap signal from said first MPU, a microprogram interruptscan in said first MPU including, a. device end prime (DEP) scanmicroprogram in each MPU, said first MPU scan trapping said second MPUto scan DEP, said second MPU setting its stat C on a detected DEP andstat D on no such detection, said first MPU repetitively scanning saidsecond MPU stats C and D until one is activated, and said second MPUwaiting said first MPU after setting either its said stats C or D, andb. additional microprograms in said MPU is said IDLESCAN interleavingstatus sensing and exchanging in accordance with said stats C and Dduring such quiescent period.
 17. The controller set forth in claim 15wherein said data flow circuits include bus connections for acontrolling and a controlled signal processing system and operative toexchange data signals therebetween, said data flow circuits includingmultimode signal processing circuits with first portions operative withsaid controlling system and second portions with said controlled system,said first and second portions being respectively controlled andactuated by microprograms in said first and second MPU''s withcoordination therebetween effected by microprograms, and said data flowcircuits including data flow status means monitoring operations of saiddata flow circuits and said data flow circuits being responsive tosignals in said first MPU exchange register means to supply statusindicating signals to said controlling system rather than data signalsfrom said controlled system.
 18. The I/O controller set forth in claim15 further including gating means interposed between a portion of saidregister means receiving signals from said first MPU and said data flowcircuits, said first MPU activating said second MPU To perform programfunctions relating to initial portions of a signal-processing operation,and said second MPU activating said gating means to initiate operationsin said data flow circuits whenever said second MPU has reached apredetermined program status in said program functions.
 19. Amicroprogrammable controller adapted to selectively connect acontrolling system to a controlled system, including the combination:first and second microprocessors (MP1 and MP2, respectively) withinterchange (IM) means for selectively transferring signalstherebetween; data flow means connected to said IM means and responsiveto first signals in said IM means to effect predetermined signalexchange between said systems and being responsive to second signals insaid IM means to generate status signals and independent means in saiddata flow means responsive to signals being processed to generateadditional status signals; MP1 having program controlled meansresponsive to signals from said controlling system to generate some ofsaid signals; MP2 having program controlled means responsive to said MP1first signals to generate the remainder of said first signals; and oneof said MP''s effecting an electrical connection between said data flowmeans and said controlled system and supplying signals to said IM meansas some of said first signals indicating an electrical connection hasbeen effected.
 20. A microprogrammable controller, including thecombination: first and second independent microprocessors includingmeans for exchanging signals therebetween, data flow circuits responsiveto said microprocessors to establish sequences of signal-processingoperations including signal waveform modifications and generatingsignals indicative of operational status including some status signalsin response to said signal-processing operations, first and secondinterface means connected to said microprocessors and said data flowcircuits for exchanging signals between different units connectable tosaid controller, and said microprocessors being constructed to receiveprograms for respectively supervising signal-exchanging operationsbetween the units respectively connectable to said interface means.